The present invention relates to an electrically programmable memory device, and more particularly to a memory device having a function for reducing power consumption upon unselection.
Various types of the electrically programmable memory devices, that is, programmable read-only memories (hereinafter abbreviated as P-ROM's), have been proposed, among them a fuse type P-ROM using a michrome line as a semi-permanent memory element (memory cell) and a junction type P-ROM using an open-base transistor as a semi-permanent memory element (memory cell).
A plurality of P-ROM's are usually used in one system such as a computer, where they are interconnected through a common data bus for the purpose of storing a necessary amount of information. Consequently, in order to read out desired information, it is necessary to make provision such that only the P-ROM storing the desired information should be selectively activated and the other P-ROM's should be inactivated so as to prevent read-out of undesired information. The selection of the desired P-ROM is performed by an external controller, and the function of inhibiting the undesired information from being output is possessed by the P-ROM itself. More particularly, a P-ROM is selected by application of a chip-enable signal from a controller, and for that purpose an output circuit is included in the P-ROM and activated by a chip-enable circuit to feed the information at the address designated by an address signal to a data bus. On the other hand, in the remaining P-ROM's which are not selected as a result of application of an unselection signal, an output level of the chip-enable circuit inactivates the output circuit, and hence output of information is inhibited.
Besides the above-described memory cell group and output circuit, the P-ROM comprises peripheral circuits such as an address circuit for receiving an address signal, a decoder for decoding the output of the address circuit to designate an addressed memory cell, and the like. Thus in an unselected P-ROM, though the output circuit is inactivated, the peripheral circuits are kept activated. Hence, the power consumption in the unselected P-ROM's is increased as the memory capacity of the device is enlarged. Consequently, in recent days a P-ROM having the so-called power-down mode has been proposed in which upon unselection not only an output circuit but also peripheral circuits are entirely or partly inactivated to reduce power consumption to less than one-half of that upon selection. More particularly, each P-ROM is provided with a power supply control circuit which inhibits power supply to the peripheral circuits when it is actuated, and this power supply control circuit is actuated upon unselection of the P-ROM. Consequently, when an unselection signal is applied to the P-ROM, simultaneously with inactivation of the output circuit, power supply from the power supply control circuit to the peripheral circuits is inhibited, so that power consumption of an unselected P-ROM can be greatly reduced.
However, although there occurs no problem in the case where a signal input terminal for activating the power supply control circuit and a chip-enable terminal for controlling activation and inactivation of an output circuit are separately provided, in the case where these terminals are provided in common there is a serious shortcoming that writing of data into the P-ROM is impossible. More particularly, a terminal for writing data into the P-ROM is normally provided in common with an output terminal in order to reduce the of a number of terminals. The output terminal is connected to a collector final stage transistor in the output circuit, and its base is furnished with information from a memory cell and is also connected to the chip-enable terminal. Accordingly, if writing of data is effected while the chip-enable terminal is maintained at a selection level, that is, while the output circuit is kept activated, then, due to the fact that the final stage transistor in the output circuit will be conducting in response to the application of a signal from a memory cell, all the writing electric power flows into the output circuit without being supplied to the memory cell, resulting in that the writing of data cannot be achieved. Therefore, upon writing of data, the output circuit must necessarily be inactivated. As described previously, inactivation of an output circuit as well as the power-down mode of the P-ROM must be achieved at the same time in order to reduce power consumption during the unselecting period. Accordingly, in the case where the signal terminal for power-down and the chip-enable terminal are provided in common, in response to application of an unselection signal level to the chip-enable terminal for inactivating the output circuit, the power supply control circuit is simultaneously actuated with the result that the peripheral circuits are also inactivated. As described above, in order to perform the writing of data it is necessary to inactivate the output circuit. This means that an unselection signal level is applied to a chip-enable terminal, so that the peripheral circuits are also inactivated simultaneously. Consequently, the writing of data would become impossible because the peripheral circuits are also inactivated simultaneously with inactivation of the output circuit.
Thus, in the conventional P-ROM, if the activation and inactivation of the output circuit as well as the power-down mode are controlled by a single common terminal, it would be impossible to write data. In other words, to realize a power-down mode of the conventional P-ROM upon unselection, a terminal for a power-down mode must be provided separately from the terminals necessitated for read-out of a program and selection of a chip. For this reason, the package of the conventional P-ROM having a power-down mode becomes large and its cost is increased.